Part¶
The part is the external device the FPGA/ASIC is communicating with. It is typically provided by a vendor.
part:
vendor: <vendor_name>
name: <part_name>
interface:
- <interface_name>:
timing_model : <interface_type>
clock:
input:
- <clock_pin_name>:
max_freq: <frequency>
output:
- <clock_pin_name>:
max_freq: <frequency>
data:
input:
- <input_pin_name>:
clock: <clock_name>
<clock_edge>:
setup:
id: <timing_id>
value: <setup_value>
hold:
id: <timing_id>
value: <hold_value>
output:
- <output_pin_name>:
clock: <clock_name>
<clock_edge>:
clock_to_out_max:
id: <timing_id>
value: <clock_to_out_max>
clock_to_out_min:
id: <timing_id>
min: <clock_to_out_min>
Example¶
The following example uses a Texas Instruments DAC81404 part.
part:
vendor: Texas Instruments
name: DAC81404
interface:
- serial_interface:
timing_model : 'source synchronous with round trip'
clock:
SCLK:
max_freq: '50 MHz'
data:
- SDIN:
falling_edge:
setup:
id: 'tSDIS'
value: '5 ns'
hold:
id: 'tSDIH'
value: '5 ns'
- SYNC_F:
falling_edge:
setup:
id: 'tCSS'
value: '20 ns'
hold:
id: 'tCSH'
value: '5 ns'
- SDO:
rising_edge:
clock_to_out:
name: 'tSDODLY'
max: '20 ns'
min: '0 ns'